1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to an integrated circuit with transistors, and to a method of making the same incorporating gate insulating layers with sloped sidewalls.
2. Description of the Related Art
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on the gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain, one implant to establish lightly doped drain structures and the other to establish overlapping heavier doped regions. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
Lightly doped drain structures ("LDD") are one of the most commonly employed semiconductor processing techniques to establish graded source/drain regions for field effect transistors. As with other types of graded drain techniques, the objective behind the incorporation of LDD structures is the reduction of gate-to-substrate potential and the resulting hot carrier phenomena that can arise in short channel devices. The first implant is performed self-aligned to the gate electrode to establish the LDD structures. After the LDD implant, dielectric sidewall spacers are formed adjacent to the gate electrode. The second of the two source/drain implants is then performed self-aligned to the sidewall spacers.
Conventional LDD/spacer processing present certain disadvantages. To begin with, LDD fabrication by ion implantation often requires at least two separate implant steps, one for the LDD structures, and one for overlapping heavier doped regions. Each implant involves separate set up and wafer handling steps, and their corresponding impacts on throughput. In addition, spacer fabrication introduces processing complexity and some potential device performance issues. Oxide based spacers are typically fabricated by first establishing a conformal layer of oxide on the gate electrode either by oxidizing the gate electrode or by blanket chemical vapor deposition ("CVD"). The conformal oxide layer is then anisotropically etched to remove oxide from the flat areas of the substrate and the gate electrode and leave spacers adjacent to the gate electrode. Silicon nitride spacers are commonly fabricated in similar fashion by blanket low pressure or plasma enhanced CVD followed by an anisotropic etch. Thermally grown oxide spacers introduce the potential for grade gate oxide ("GGO") fingers to form and penetrate laterally at the gate-gate oxide interface. GGO fingers can cause undesirable gaps between the edges of the LDD structures and the edges of the gate electrode, which may lead to a weak overlap condition. Even larger gaps will arise between the edges of the heavier doped regions of the source/drain regions and the edges of the gate electrode. Although a deep drive anneal may reduce the widths of the gaps, such a high temperature step may lead to source/drain junctions with depths that are unsuitable for a transistor, particularly if implemented in CMOS. This problem may be present even if CVD oxide is used for spacers in situations where a poly-reoxidation step precedes the CVD oxide step.
The CVD oxide step to create silicon dioxide spacers typically produces a thicker oxide film at the edge of the gate-to-active area step than on flat areas. Thus, a subsequent anisotropic dry-etch process will clear the oxide in the flat areas while leaving spacers at the sidewalls of the poly gate. Some overetch is almost always necessary to account for variations in the spacer oxide layer thickness. The overetch frequently consumes some of the silicon substrate in the source/drain regions as well as any surrounding isolation structures, such as field oxide and/or shallow trench isolation material. Excessive overetching of these regions is undesirable from both device isolation and junction leakage standpoints.
In addition to the drawbacks associated with conventional LDD/spacer fabrication, various aspects of gate dielectric formation in conventional transistor fabrication present disadvantages. Silicon dioxide gate oxide layers are made as thin as possible to maximize drive current and to control short channel effects. The requirement for very thin gate oxide layers has become particularly important in sub-micron processing where process scaling has dramatically increased the potential for short channel effects. However, the scaling of silicon dioxide gate dielectric layers has introduced another set of problems. To begin with, very thin silicon dioxide layers have been historically difficult to fabricate with a consistent thickness across a given wafer, from wafer to wafer and from lot to lot. In addition, as the thickness of silicon dioxide is scaled downward, the potential for reliability problems associated with dielectric breakdown and hot-carrier-injection degradation increases. Hot carrier degradation can significantly reduce device performance, while dielectric breakdown can lead to complete device failure.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.